This invention relates generally to sample rate converters and in particular to cascaded integrator-comb (CIC) filters used in sample rate conversion applications, and is more particularly directed toward a resampling CIC filter that interpolates or decimates a signal by a factor of M/N. For an interpolator N may be a rational number whilst M may be a natural number. For a decimator M may be a rational number whilst N may be a natural number.
Historically, data rate conversions have ranged from simple compression and expansion of digital data streams to actual sample rate multiplication suitable for oversampling data conversion applications. In modern systems, sample rate conversion is an integral aspect of transmitter and receiver signal processing ICs (integrated circuits) designed for baseband and IF signal processing for digital modulation schemes.
Early data rate adjustment mechanisms, such as that disclosed in U.S. Pat. No. 4,893,339, to Bright et al., were often employed so that portions of a digital data stream could be replaced with other information without altering the net data rate. Similar schemes are also used in telephony to accommodate certain types of signaling bits.
In the Bright et al. patent, bits are discarded periodically from an input data stream in order to make room for a necessary block of additional data bits. Fortunately, because of inherent redundancy in the relatively low rate voice coder of Bright et al., little significant information is lost during the compression operation. At the receiver, the original voice stream is reconstructed by simple bit insertion using an empirically derived algorithm. Simple digital companding schemes such as this do not work well with more complex voice coders, such as LPC (linear predictive coding) based coders.
As noted, oversampling data conversion systems generally include an interpolator that increases the sampling rate of a digital input sample stream. Interpolation generally consists of taking one sequence a(n) and producing another sequence b(m) whose samples occur r times as fast. Interpolation is a necessary step in sigma-delta conversion systems that operate on a high frequency bit stream.
As data conversion systems become faster and faster, narrow-band extraction from wideband sources is becoming commonplace, as is wideband construction of narrow-band signals. It has become commonplace to implement sample rate conversion by integer factors using cascaded integrator-comb (CIC) filters to perform basic interpolation and decimation operations. The use of CIC techniques facilitates conversion between multiple sample rates, without the need for multiple filters in hardware, where each value of rate change requires a different filter to be realized.
In order to facilitate a rational rate change of M/N, an integer interpolator by M is cascaded with an integer decimation of N. Prior art systems generally permit rate conversions by a factor of M/N, where both M and N are constrained to be natural numbers. For systems with a large number of selectable input and output sample rates, an integer constraint on both M and N can result in values well into the millions, with unworkably large bit growth. Consequently, a need arises for an efficient and realistic implementation that will provide an M/N rate change with N rational for an interpolating SRC (sample rate converter) or M rational for a decimating SRC.
These needs and others are satisfied by the sample rate converter of the present invention. The discussion of the present invention focuses on an interpolating SRC, but a decimating SRC based upon the same principles has also been demonstrated.
The SRC 301 (FIG. 3) of the present invention was developed to implement a rate change of M/N using a very efficient design implementation. For the digital signal processing datapaths described herein, there are 11 different sample rates at the output 303 of the interpolating SRC 301 that must be matched to one of 9 sample rates at the input 302. The input and output sample rates are shown in the table of FIG. 4. Constraining M and N to integer values would yield values well into the millions, with concomitant unworkably large bit growth. As an example, rate converting 44.1 kHz*32 at the input to 13 MHz/5 at the output would require M=104000, and N=56448.
Allowing multiple, selectable values for M in the interpolator, or N in the decimator, requires different filter characteristics. Rather than implement several individual filters, the CIC approach locates the pole and zeros as a consequence of the algorithm.
The solution described utilizes a CIC-based interpolating sample rate converter with noise-shaped control of the N value. For a decimator, noise-shaped control of the M value is utilized. In the interpolator, the N value is the correct value on average, but demonstrates instantaneous errors that must be noise-shaped. This is an example of so-called xe2x80x9cnon-uniformxe2x80x9d resampling. The CIC SRC implementation capitalizes on the fact that the outputs of the CIC that are discarded during downsampling need not be calculated by the CIC in the first instance. The combination of the computational simplicity of CIC SRC with noise-shaped, non-uniform resampling performs the sample rate conversion very economically.
A CIC interpolator in conjunction with a downsampler, to form an interpolating SRC, is illustrated in block diagram form in FIG. 5. As shown, the CIC filter 501 upsamples the input data stream 502 by a factor of M, and displays a filter power spectrum proportional to sinc2. The reshaped, upsampled signal is then downsampled by N to produce the output data stream 503.
As illustrated in FIG. 6, the interpolating SRC operates on the input data stream 601 through differentiate 603 and hold 604 sections, at the input rate, then the integrate and decimate section 605 operates on the data stream to produce output samples at the output rate.
The timing diagram of FIG. 7 illustrates the values by which the DN values 701 of the input data stream are multiplied. M is equal to 441, while the instantaneous N values are 183, 185, and 183. The values by which the DN are multiplied (183, 185, 73, as illustrated) are calculated on-the-fly, as the numbers are supplied by the associated digital sigma-delta modulator (606 in FIG. 6) so as to fix the location of the pole and zeroes of the interpolator""s transfer function. Conceptually, the interpolation achieved by the CIC is fixed (441, in the example shown) while the downsampling varies instantaneously without affecting the operation of the CIC.
In accordance with one aspect of the present invention, an improved interpolating sample rate converter is provided that operates on an input data stream to perform upsampling, filtering, and downsampling of the input data stream to produce an output data stream having a higher sample rate than the input data stream. A cascaded integrator-comb filter performs at least a part of the upsampling and filtering of the input data stream, and downsampling is conducted at an instantaneously variable rate. Downsampling may be conducted at an instantaneously variable rate through a digital sigma-delta modulator that controls downsampling on a sample-by-sample basis to implement non-uniform downsampling. Preferably, the output of the sigma-delta modulator is divided to provide a clock signal having a fixed frequency and a non-uniform period.
In accordance with another aspect of the present invention, an improved decimating sample rate converter is provided that operates on an input data stream to perform upsampling, filtering, and downsampling of the input data stream to produce an output data stream having a lower sample rate than the input data stream. A cascaded integrator-comb filter performs at least a part of the filtering and downsampling of the input data stream, and upsampling is conducted at an instantaneously variable rate. Upsampling may be conducted at an instantaneously variable rate through a digital sigma-delta modulator that controls upsampling on a sample-by-sample basis to implement non-uniform upsampling. Preferably, the output of the sigma-delta modulator is divided to provide a clock signal having a fixed frequency and a non-uniform period.
In accordance with yet another aspect of the present invention, an interpolating sample rate converter that provides rate conversion by a factor of M/N comprises an upsampler that upsamples an input data stream by a factor of M, a filter that shapes the upsampled data stream in accordance with a predetermined power spectrum, and a downsampler that downsamples the upsampled and shaped signal by a factor of N to produce an output data stream. The upsampler and filter are implemented, at least in part, by a cascaded integrator-comb filter. The upsampling factor M is an integer and the downsampling factor N is not an integer. Preferably, the predetermined power spectrum is proportional to sinc2.
In accordance with still another aspect of the present invention, the interpolating sample rate converter further comprises a sigma-delta modulator that provides noise-shaped control of the N value for the downsampler. Preferably, the sigma-delta modulator controls downsampling on a sample-by-sample basis to implement non-uniform downsampling. The output of the sigma-delta modulator may be divided to provide a clock signal having a fixed frequency and a non-uniform period.
In accordance with yet a further aspect of the present invention, a decimating sample rate converter that provides rate conversion by a factor of M/N comprises an upsampler that upsamples an input data stream by a factor of M, a filter that shapes the upsampled data stream in accordance with a predetermined power spectrum, and a downsampler that downsamples the upsampled and shaped signal by a factor of N to produce an output data stream. The filter and downsampler are implemented, at least in part, by a cascaded integrator-comb filter. The upsampling factor M is not an integer and the downsampling factor N is an integer. Preferably, the predetermined power spectrum is proportional to sinc2.
In another form of the invention, the decimating sample rate converter further comprises a sigma-delta modulator that provides noise-shaped control of the M value for the upsampler. Preferably, the sigma-delta modulator controls upsampling on a sample-by-sample basis to implement non-uniform upsampling. The output of the sigma-delta modulator may be divided to provide a clock signal having a fixed frequency and a nonuniform period.
In accordance with still another aspect of the invention, a method for sample rate conversion of a digital input signal comprises the steps of providing an input digital data stream at an input sample rate, filtering and interpolating the input digital data stream by an integer value I utilizing, at least in part, a cascaded integrator-comb filter, and decimating the interpolated input digital data stream by an instantaneously variable value V to provide an output digital data stream at an output sample rate. The step of decimating the interpolated input digital data stream by an instantaneously variable value V may further comprise the step of deriving the instantaneously variable value V through a digital sigma-delta modulator that controls downsampling on a sample-by-sample basis to implement non-uniform downsampling.
In accordance with yet a further aspect of the present invention, a method for sample rate conversion of a digital input signal comprises the steps of providing an input digital data stream at an input sample rate, interpolating the input digital data stream by an instantaneously variable value V, and filtering and decimating the interpolated input digital data stream by a value I utilizing, at least in part, a cascaded integrator-comb filter, to provide an output digital data stream at an output sample rate. The step of interpolating the input digital data stream by an instantaneously variable value V may further comprise the step of deriving the instantaneously variable value V through a digital sigma-delta modulator that controls upsampling on a sample-by-sample basis to implement non-uniform upsampling.
In accordance with yet another aspect of the invention, a sample rate converter for a digital input signal comprises means for providing an input digital data stream at an input sample rate, means for filtering and interpolating the input digital data stream by an integer value I utilizing, at least in part, a cascaded integrator-comb filter, and means for decimating the interpolated input digital data stream by an instantaneously variable value V to provide an output digital data stream at an output sample rate The means for decimating the interpolated input digital data stream by an instantaneously variable value V may comprise means for deriving the instantaneously variable value V through a digital sigma-delta modulator means that controls downsampling on a sample-by-sample basis to implement non-uniform downsampling.
In accordance with still a further aspect of the invention, a sample rate converter for a digital input signal comprises means for providing an input digital data stream at an input sample rate, means for interpolating the input digital data stream by an instantaneously variable value V, and means for filtering and decimating the interpolated input digital data stream by a value I utilizing, at least in part, a cascaded integrator-comb filter, to provide an output digital data stream at an output sample rate. The means for interpolating the input digital data stream by an instantaneously variable value V may comprise means for deriving the instantaneously variable value V through a digital sigma-delta modulator means that controls upsampling on a sample-by-sample basis to implement non-uniform upsampling.